Reproducing capacitive cyclic voltammetric curves by simulation: When are simplified geometries appropriate?

The usage of multi-physics simulation tools is steadily increasing in the field of electrochemistry. While this is a great opportunity for closing the gap between analytical electrochemists used to simple 1D models and exper-imentalists, there are possible pitfalls that must be avoided. In this work, we raise awareness on numerical ar-tifacts that can mislead the interpretation of cyclic voltammetry experiments through simulations of geometries with different number of spatial dimensions. In particular, we show that one-dimensional simulations can suffer from substantial errors when models go beyond charge neutrality assumption. We exemplify such situations using simple electrolyte/electrode structures with 1D, 2D and 3D geometries. We then show the occurrence of artifacts related to the geometry of the simulation domain on the simulation of cyclic voltammetric curves as those typically performed to characterize conjugated polymer/electrolyte blends. All the models are imple-mented using COMSOL Multiphysics and are accompanied by a detailed description of their implementation. However, geometrical artifacts identified in this work also apply to other simulation approaches

General model and equivalent circuit for the chemical noise spectrum associated to surface charge fluctuation in potentiometric sensors

This paper firstly reports a general and powerful approach to evaluate the power spectral density (PSD) of the surface charge fluctuations, so-called \u201cchemical noise\u201d, from a generic set of reactions at the sensing surface of potentiometric sensors such as, for instance, Ion-Sensitive Field Effect Transistors (ISFETs). Starting from the master equation, the spectral noise signature of a reaction set is derived as a function of the reaction kinetic parameters and of the interface concentration of the ionic species. Secondly, we derive an equivalent surface admittance, whose thermal noise PSD produces a noise PSD equal to that of the surface charge fluctuations. We also show how to expand this surface admittance into stair-case RC networks, with a number of elementary cells equal to the number of surface reactions involved. This admittance can be included in circuit simulations coupled with a SPICE compact model of the underlying FET, to enable the physically based modelling of frequency dispersion and noise of the sensing layer when simulating the sensor and the read-out. Validation with existing models and literature results as well as new application examples are provided. The proposed methodology to compute the PSD from rate equations is amenable to use in different contexts where fluctuations are generated by random transitions between discrete states with given exchange rates

General Approach to Model the Surface Charge Induced by Multiple Surface Chemical Reactions in Potentiometric FET Sensors

We propose a general methodology to calculate the individual sensitivity and the cross-sensitivities of potentiometric sensor devices (e.g., ion sensitive FETs (ISFETs), CHEMFETs) with an arbitrary number of non-interacting receptors binding to ionic species or analytes in the electrolyte. The surface charge generated at the (bare or functionalized) interface with the electrolyte is described by the Poisson equation coupled to a linear system of equations for each type of receptor, where the unknowns are the fractions of sites binding with a given ion/analyte. Our general model encompasses in a unique framework a few simple special cases so far separately reported in the literature and provides for them closed-form expressions of the average site occupation probability. Detailed procedural description of the usage and benefits of the model is shown for specific cases with concurring surface chemical reactions

Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs

NTRODUCTION \u2015 In the past decade the Tunnel Field Effect Transistor (TFET) relying on band-to-band tunneling (BTBT) has emerged as one of the most promising small slope FETs able to achieve a subthreshold swing (SS) below the room temperature 60 mV/dec limit of conventional MOSFET [1]. Many simulation studies attributed to TFETs the potential to outperform conventional MOSFETs in the ultra-low voltage domain (VDD < 0.4 V) in both analog [2-3] and digital [4-7] applications. However, only basic digital and analog circuits have been fabricated up to date, such as current mirrors [8] and inverter gates [9]. As for semiconductor materials, III-V hetero-structure TFETs may be able to achieve a sub-thermal SS in a wide current range and, at the same time, very competitive on currents [1], as demonstrated by a recently fabricated vertical InAs/GaAsSb/GaSb nanowire n-type TFETs [10]. The aim of this work is to benchmark a complementary III-V TFET technology platform against the mainstream FinFET reference, by considering basic building blocks of digital and analog applications. To this purpose, we selected a complementary III-V TFET technology platform designed and optimized using full quantum simulations in [11], where n- and p-type TFET pairs are realized in the same InAs/AlGaSb material system. The use of such devices allowed us to remove the excessively optimistic assumption of perfectly symmetric n- and p-type TFETs, very frequently embraced in previous simulation studies (e.g. in [2, 7]). We present circuit-level simulations performed on current mirrors and inverter-based logic blocks, which are identified as basic topologies representative of the analog and digital design realms, respectively. Similar benchmarking results for the same technology platforms have been obtained by focusing the comparison on more complicated circuit blocks [3], [5] and [6]

Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits

In this work, a complementary InAs/Al0.05Ga0.95Sb tunnel field-effect-Transistor (TFET) virtual technology platform is benchmarked against the projection to the CMOS FinFET 10-nm node, by means of device and basic circuit simulations. The comparison is performed in the ultralow voltage regime (below 500 mV), where the proposed III-V TFETs feature ON-current levels comparable to scaled FinFETs, for the same low-operating-power OFF-current. Due to the asymmetrical n-and p-Type I-V exts , trends of noise margins and performances are investigated for different Wp/Wn ratios. Implications of the device threshold voltage variability, which turned out to be dramatic for steep slope TFETs, are also addressed

Electromechanical Piezoresistive Sensing in Suspended Graphene Membranes

Monolayer graphene exhibits exceptional electronic and mechanical properties, making it a very promising material for nanoelectromechanical (NEMS) devices. Here, we conclusively demonstrate the piezoresistive effect in graphene in a nano-electromechanical membrane configuration that provides direct electrical readout of pressure to strain transduction. This makes it highly relevant for an important class of nano-electromechanical system (NEMS) transducers. This demonstration is consistent with our simulations and previously reported gauge factors and simulation values. The membrane in our experiment acts as a strain gauge independent of crystallographic orientation and allows for aggressive size scalability. When compared with conventional pressure sensors, the sensors have orders of magnitude higher sensitivity per unit area.Comment: 20 pages, 3 figure

Understanding the Excess 1/f Noise in MOSFETs at Cryogenic Temperatures

Characterization, modeling, and development of cryo-temperature CMOS technologies (cryo-CMOS) have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface in quantum computers. Nevertheless, available compact models still fail to predict the deviation of 1/f noise from the expected linear scaling with temperature ( $\textit{T}$ ), referred to as “excess 1/f noise”, observed at cryogenic temperatures. In addition, 1/f noise represents one of the main limiting factors for the decoherence time of qubits. In this article, we extensively characterize low-frequency noise on commercial 28-nm CMOS and on research-grade Ge-channel MOSFETs at temperatures ranging from 370 K down to 4 K. Our investigations exclude electron heating and bulk dielectric defects as possible causes of the excess 1/f noise at low temperatures. We show further evidence for a strong correlation between the excess 1/f noise and the saturation of the subthreshold swing (SS) observed at low temperatures. The most plausible cause of the excess noise is found in band tail states in the channel acting as additional capture/emission centers at cryogenic temperatures

Sensitivity, noise and resolution in a beol-modified foundry-made isfet with miniaturized reference electrode for wearable point-of-care applications

Ion-sensitive field-effect transistors (ISFETs) form a high sensitivity and scalable class of sensors, compatible with advanced complementary metal-oxide semiconductor (CMOS) processes. Despite many previous demonstrations about their merits as low-power integrated sensors, very little is known about their noise characterization when being operated in a liquid gate configuration. The noise characteristics in various regimes of their operation are important to select the most suitable conditions for signal-to-noise ratio (SNR) and power consumption. This work reports systematic DC, transient, and noise characterizations and models of a back-end of line (BEOL)-modified foundry-made ISFET used as pH sensor. The aim is to determine the sensor sensitivity and resolution to pH changes and to calibrate numerical and lumped element models, capable of supporting the interpretation of the experimental findings. The experimental sensitivity is approximately 40 mV/pH with a normalized resolution of 5 mpH per \ub5m2, in agreement with the literature state of the art. Differences in the drain current noise spectra between the ISFET and MOSFET configurations of the same device at low currents (weak inversion) suggest that the chemical noise produced by the random binding/unbinding of the H+ ions on the sensor surface is likely the dominant noise contribution in this regime. In contrast, at high currents (strong inversion), the two configurations provide similar drain noise levels suggesting that the noise originates in the underlying FET rather than in the sensing region

Digital and analog TFET circuits: Design and benchmark

In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDDlower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions